Phased locked loop circuit including voltage controlled ring oscillator

ABSTRACT

There is provided a voltage controlled ring oscillator having a plurality of ring-connected amplifiers ( 401 ), and a plurality of variable capacitance elements ( 502   a   , 502   b ) being respectively connected to the plurality of amplifiers and having capacitances varied by a voltage control. A plurality of load resistors ( 402 ) and a plurality of tail current sources ( 403 ) are respectively connected to the plurality of amplifiers.

CROSS-REFERENCE TO RELATED APPLICATION

This is a National Stage entry of International Application No.PCT/JP2005/023384, filed Dec. 20, 2005. The disclosure of the priorapplication is hereby incorporated herein in its entirety by reference.

TECHNICAL FIELD

The present invention relates to a voltage controlled ring oscillator.

BACKGROUND ART

FIG. 14A is a view showing a structural example of a voltage controlledring oscillator. The voltage controlled ring oscillator is a VoltageControlled Oscillator (VCO). A plurality of differential amplifiers 1401are ring-connected. A plurality of variable resistors 1402 arerespectively connected to the plurality of differential amplifiers 1401.A plurality of current sources 1403 are respectively connected to theplurality of differential amplifiers 1401. A CR ring element 1404 haseach one of the differential amplifier 1401, the variable resistor 1402,and the current source 1403. Four of the CR ring elements 1404 arering-connected, for instance.

FIG. 14B is a circuit diagram showing a structural example of the CRring element 1404 in FIG. 14A. The CR ring element 1404 has a bias unit1431 and an oscillating unit 1432. Hereinafter, an MOS field-effecttransistor is simply referred to as a transistor. The bias unit 1431 hasa P-channel transistor 1411 and an N-channel transistor 1412.

The oscillating unit 1432 inputs differential signals from anon-inverting input terminal I+ and an inverting input terminal I− toamplify them, and outputs the amplified differential signals from anon-inverting output terminal O+ and an inverting output terminal O−.The differential signals are two signals whose phases are mutuallyinverted by 180°. The N-channel transistor 1422 corresponds to thecurrent source 1403 in FIG. 14A, and constitutes a current mirrorcircuit with the transistor 1412. When a current Il flows through thetransistor 1412, a current Is flows through the transistor 1422. To thenon-inverting output terminal O+ and the inverting output terminal O−, aparasitic capacitance 1425 b and a parasitic capacitance 1425 a arerespectively connected. The non-inverting input terminal I+ is connectedto a gate of an N-channel transistor 1421 a, and the inverting inputterminal I− is connected to a gate of an N-channel transistor 1421 b.P-channel transistors 1424 a and 1423 a are connected to the transistor1421 a, and constitute a load resistor. P-channel transistors 1424 b and1423 b are connected to the transistor 1421 b, and constitute a loadresistor. The transistors 1423 a and 1423 b are variable resistorscontrolled by a voltage Vcntl. In the CR ring element 1404, a delayamount of the output signal is determined by a CR, that is, acapacitance and a resistor. By varying the variable resistors 1423 a and1423 b with the voltage Vcntl, an oscillation frequency of the ringoscillator can be controlled.

As described above, the voltage controlled ring oscillator is composedof the oscillating unit 1432 which applies positive feedback byconnecting a plurality of stages of Current Mode Logic (CML)-type ringelements (CR delay elements), and the bias unit 1431 which supplies abias voltage to the ring elements. The control voltage Vcntl is inputinto the bias unit 1431, and the bias unit 1431 outputs the bias voltagewhich is in proportion to the voltage Vcntl. The bias voltage controls atail current source 1422 and the transistors 1423 a and 1423 b being theload resistors in a CML circuit. There is a method for controlling onlyeither the load resistors 1423 a and 1423 b or the tail current source1422, but, in order to make an amplitude constant without depending onthe oscillation frequency, a method for controlling both of them iscommonly adopted.

FIG. 15 is a graph showing a relation between the control voltage Vcntland the oscillation frequency fosc. Since the control voltage Vcntl iscontrolled after passing through one stage of the transistor 1411 in thebias unit 1431, it is affected by a threshold voltage Vth of thetransistor. The transistor 1411 is connected at a source thereof to apower supply voltage Vdd, and connected at a drain thereof to a gate ofthe transistor 1422. In the ring oscillator, there is a problem that thethreshold voltage Vth becomes a hindrance for obtaining a tuning range,so that the tuning range has to be secured with the voltage in which thethreshold voltage Vth is subtracted from the power supply voltage Vdd.The tuning range of the control voltage Vcntl required to realize atarget oscillation frequency 1501 which meets the specifications, is atuning range 1502. Depending on a process variation and the like, acharacteristic varies between a characteristic FAST and a characteristicSLOW. A characteristic TYP is a typical characteristic when thethreshold voltage Vth takes a typical value. The characteristic FAST isa characteristic when the threshold voltage Vth varies at lowfrequencies. The characteristic SLOW is a characteristic when thethreshold voltage Vth varies at high frequencies. The ring oscillator isaffected largely by the process variation.

When trying to secure the target tuning range 1502 by including theprocess variation and variations of the power supply voltage Vdd, atemperature, and the like, the minimum of the characteristic isdetermined at the characteristic SLOW with the narrowest band, whichconsequently brings about a problem that a gain of the VCO becomes veryhigh at the characteristic TYP. The gain of the VCO corresponds to aninclination of the characteristic. When the gain of the VCO isincreased, the VCO itself becomes highly sensitive, so that it is forcedto respond sensitively to the power supply voltage variation and thevariation of the control voltage Vcntl. This leads to generate a jitter,which deteriorates the performance of a PLL (Phase Locked Loop) circuitwhen the VCO is applied thereto.

Further, along with the advance in technology, a voltage scaling(lowering the voltage) is in progress. In the ring oscillator, thevoltage scaling is a big problem. While the power supply voltage isscaled, the threshold voltage Vth of the transistor is not scaled, sothat the value Vdd-Vth being the tuning range 1502 becomes smaller. Whena circuit is composed using a voltage of 1V or lower in the future, thetuning range 1502 cannot be secured by an existing circuit system, whichcan be easily predicted.

As described above, since the tuning range 1502 is determined by a valueVdd-Vth, the existing ring oscillator has dealt with it by increasingthe gain of the VCO. However, to increase the gain of the VCO means tosimultaneously increase a noise (jitter), and it also suggests that thedesign becomes further difficult to cope with the power supply voltagescaling in the future.

Further, an electrostatic capacitance type weight sensor is knownwherein the sensor has a variable capacitor formed of a fixed electrodeand a movable electrode in which a capacitor having a predeterminedelectrostatic capacitance is inserted between a fixing metal frame andthe fixed electrode, to thereby largely reduce a variation ofoscillation frequency offset values and the sensitivity variation causedby a stray capacitance depending on an environmental change and a changewith time.

Further, a self-excited oscillation circuit is known wherein theoscillation circuit has a CR oscillating unit in which a variablecapacitance diode is used.

Furthermore, a ring oscillator is known in which a plurality ofdifferential gain stages are connected in a ring shape via resistorelements, and a band-pass filter is respectively connected between eachof inputs of the differential gain stages and a reference potential.

SUMMARY

According to one aspect of the present invention, there is provided avoltage controlled ring oscillator having a plurality of ring-connectedamplifiers and a plurality of variable capacitance elements beingrespectively connected to the plurality of amplifiers and havingcapacitances varied by a voltage control.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view showing a structural example of a high speedinput/output (I/O) circuit according to a first embodiment of thepresent invention;

FIG. 2 is a circuit diagram showing a structural example of a VCO inFIG. 13;

FIG. 3 is a sectional view of a semiconductor chip showing a structuralexample of a variable capacitance in FIG. 5;

FIG. 4 is a circuit diagram showing a structural example of a VCO inFIG. 1;

FIG. 5 is a circuit diagram showing a structural example of a CR ringelement in FIG. 4;

FIG. 6 is a graph showing a relation between a both-end voltage Vvar anda capacitance Cvar of a variable capacitance;

FIG. 7 is a graph showing a relation between a control voltage Vcntl andan oscillation frequency fosc;

FIG. 8A is a block diagram showing a structural example of a PLL circuitaccording to a second embodiment of the present invention;

FIG. 8B is a circuit diagram showing a structural example of a VCO inFIG. 8A;

FIG. 8C is a circuit diagram showing a structural example of a CR ringelement in FIG. 8B;

FIG. 9A is a block diagram showing a structural example of a PLL circuitaccording to a third embodiment of the present invention;

FIG. 9B is a circuit diagram showing a structural example of a VCO inFIG. 9A;

FIG. 9C is a circuit diagram showing a structural example of a CR ringelement in FIG. 9B;

FIG. 9D is a view showing a structural example of a load resistor unitin FIG. 9C;

FIG. 9E is a view showing another structural example of the loadresistor unit in FIG. 9C;

FIG. 9F is a view showing still another structural example of the loadresistor unit in FIG. 9C;

FIG. 10A is a block diagram showing a structural example of a PLLcircuit according to a fourth embodiment of the present invention;

FIG. 10B is a circuit diagram showing a structural example of a VCO inFIG. 10A;

FIG. 10C is a circuit diagram showing a structural example of a CR ringelement in FIG. 10B;

FIG. 10D is a view showing a structural example of a load resistor unitin FIG. 10C;

FIG. 10E is a view showing another structural example of the loadresistor unit in FIG. 10C;

FIG. 10F is a view showing still another structural example of the loadresistor unit in FIG. 10C;

FIG. 11A is a block diagram showing a structural example of a PLLcircuit according to a fifth embodiment of the present invention;

FIG. 11B is a circuit diagram showing a structural example of a VCO inFIG. 11A;

FIG. 11C is a circuit diagram showing a structural example of a CR ringelement in FIG. 11B;

FIG. 11D is a view showing a structural example of a load resistor unitin FIG. 11C;

FIG. 11E is a view showing a structural example of a tail current sourcein FIG. 11C;

FIG. 12A is a block diagram showing a structural example of a PLLcircuit according to a sixth embodiment of the present invention;

FIG. 12B is a circuit diagram showing a structural example of a VCO inFIG. 12A;

FIG. 12C is a circuit diagram showing a structural example of a CR ringelement in FIG. 12B;

FIG. 12D is a view showing a structural example of an offset capacitancein FIG. 12C;

FIG. 12E is a view showing another structural example of the offsetcapacitance in FIG. 12C;

FIG. 13 is a block diagram showing a structural example of a PLL circuitaccording to a seventh embodiment of the present invention;

FIG. 14A is a view showing a structural example of a voltage controlledring oscillator;

FIG. 14B is a circuit diagram showing a structural example of a CR ringelement in FIG. 14A; and

FIG. 15 is a graph showing a relation between a control voltage Vcntland an oscillation frequency fosc.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a view showing a structural example of a high speedinput/output (I/O) circuit according to a first embodiment of thepresent invention. In case of the high speed I/O circuit, a frequencyclock being half of the data rate is required from a driver (Tx) and areceiver (Rx), in which the clock is generated by a PLL circuit 110. ThePLL circuit 110 has a phase detector 101, a charge pump 102, a loopfilter (LPF) 103, a voltage controlled oscillator (VCO) 104, and amultiplier 105. The phase detector 101 compares a reference clock RCLKwith an output clock (feedback clock) output from the multiplier 105,and then outputs a pulse width corresponding to the phase error to thecharge pump 102. The charge pump 102 flows a current corresponding tothe pulse width through the LPF 103. The LPF 103 is a low-pass filterwhich smoothes the error signal. The VCO 104 oscillates in accordancewith the smoothed voltage Vcntl, and outputs I signals and Q signals.For instance, the I signals are differential signals of 0° and 180°, andthe Q signals are differential signals of 90° and 270°. The multiplier105 outputs a signal in which a frequency of one signal output from theVCO 104 is multiplied by N to the phase detector 101. As a result, whenthe phase error detected by the phase detector 101 becomes 0, the PLLcircuit 110 shifts to a locked state (stationary state), which enablesto obtain a stable synchronous clock (I signals and Q signals) in whichthe frequency of the reference clock RCLK is multiplied by N.

A phase interpolator 106 mixes output signals from the VCO 104 and adigital filter 109, and outputs to a decision latch 107. The decisionlatch 107 latches serial-format data Din, and outputs it to ademultiplexer 108. The demultiplexer 108 converts the data from serialformat to parallel format, to thereby output data Dout. The digitalfilter 109 filters the output data of the demultiplexer 108, and outputsto the phase interpolator 106. Accordingly, the latch timing of thedecision latch 107 can be adjusted to be an appropriate timing in whichthe data Din is stable.

For the VCO 104 applied to the high speed I/O circuit, an LC-type VCOusing an LC resonance or a voltage controlled ring oscillator applyingpositive feedback to differential CML-type amplifiers is used.Especially, in a PLL circuit which is not intended to be used at RF band(several GHz over), or which is intended to reduce the cost by usingnone of the specific elements such as an inductor, the voltagecontrolled ring oscillator is used.

Further, along with an advance in technology in recent years, themovement toward lowering the voltage is in progress. Although a digitalcircuit has a margin in low voltage specifications since a circuitoperation thereof is determined by a logical threshold value, thisvoltage scaling occurs various troubles in an analog circuit. Anapplicable range of the present invention includes the high speed I/Ocircuit, the VCO 104 used for low voltage specifications, the PLLcircuit 110 using the VCO 104, and the like.

FIG. 4 is a circuit diagram showing a structural example of the VCO 104in FIG. 1. This VCO 104 is a voltage controlled ring oscillator. Aplurality of differential amplifiers 401 are ring-connected. A pluralityof load resistors 402 are fixed resistors respectively connected to theplurality of differential amplifiers 401. A plurality of current sources403 are constant current sources respectively connected to the pluralityof differential amplifiers 401. A CR ring element 404 has each one ofthe differential amplifier 401, the load resistor 402, and the currentsource 403. Four of the CR ring elements 404 are ring-connected, forinstance. The differential amplifier 401 inputs differential signals,amplifies them and outputs. The differential signals are two signalswhose phases are mutually inverted by 180°. Output differential signalsof the respective differential amplifiers 401 have phase differences inwhich one period is divided by the number of differential amplifiers401. For instance, the second differential amplifier 401 from the rightoutputs the differential signals of 0° and 180° as an I signal. Thedifferential amplifier 401 on the far left outputs the differentialsignals of 90° and 270° as a Q signal. The differential amplifier 401has a variable capacitance which is controlled by the control voltageVcntl.

FIG. 5 is a circuit diagram showing a structural example of the CR ringelement 404 in FIG. 4. The CR ring element 404 has a CML-typedifferential amplifier in which the differential signals are input froma non-inverting input terminal I+ and an inverting input terminal I−,and after being amplified, the differential signals are output from anon-inverting output terminal O+ and an inverting output terminal O−. Aconstant current Is is flown through the current source 403. To thenon-inverting output terminal O+ and the inverting output terminal O−, aparasitic capacitance 503 b and a parasitic capacitance 503 a arerespectively connected. The non-inverting input terminal I+ is connectedto a gate of an N-channel transistor 501 a, and the inverting inputterminal I− is connected to a gate of an N-channel transistor 501 b. Theinverting output terminal O− is connected to a drain of the transistor501 a. The non-inverting output terminal O+ is connected to a drain ofthe transistor 501 b. The current source 403 is connected between aninterconnection point of sources of the transistors 501 a and 501 b anda ground. A load resistor 402 a is connected between the drain of thetransistor 501 a and a power supply voltage. A load resistor 402 b isconnected between the drain of the transistor 501 b and the power supplyvoltage. A variable capacitance 502 a is connected between the drain ofthe transistor 501 a and the control voltage Vcntl. A variablecapacitance 502 b is connected between the drain of the transistor 501 band the control voltage Vcntl. The variable capacitances 502 a and 502 bare on-chip varactors (varicaps). In the CR ring element 404, a delayamount of the output signal is determined by a CR, that is, acapacitance and a resistor. By varying the variable capacitances 502 aand 502 b with the voltage Vcntl, an oscillation frequency of the ringoscillator can be controlled.

FIG. 3 is a sectional view of a semiconductor chip showing a structuralexample of the respective variable capacitances 502 a and 502 b in FIG.5. The variable capacitances 502 a and 502 b are formed on thesemiconductor chip. A basic structure of the variable capacitances 502 aand 502 b is based on a structure of a transistor. A P-typesemiconductor substrate 301 is a silicon substrate, for instance. AnN-type well 302 is formed on the P-type substrate 301. N⁺-type regions303 and 305 correspond to a source and a drain of a transistor, and areformed on a surface of the N-type well 302 by ion injection. A region307 corresponds to a channel region of the transistor, and is formed onthe surface of the N-type well 302 by ion injection. A dielectric layer308 corresponds to a gate oxide film of the transistor, and is formed onthe region 307 using a silicon oxide film. A polysilicon 309 is formedon the dielectric layer 308. A contact portion 310 is formed on thepolysilicon 309, and is connected to a terminal 311. The terminal 311 isconnected to the drain of either the transistor 501 a or the transistor501 b. A contact portion 304 is formed on the N⁺-type region 303. Acontact portion 306 is formed on the N⁺-type region 305. The contactportions 304 and 306 are connected to the control voltage Vcntl.

FIG. 6 is a graph showing a relation between both-end voltages Vvar andcapacitances Cvar of the variable capacitances 502 a and 502 b in FIG.5. The capacitance Cvar can be controlled by varying the both-endvoltage Vvar. The both-end voltage Vvar can take a range 601 from thepower supply voltage Vdd to −Vdd as a tuning range. The both-end voltageVvar can be controlled by the control voltage Vcntl, so that it is neveradversely affected by a threshold voltage Vth as shown in FIG. 15.

FIG. 7 is a graph showing a relation between the control voltage Vcntland an oscillation frequency fosc. Depending on a process variation andthe like, a characteristic varies between a characteristic FAST and acharacteristic SLOW. A characteristic TYP is a characteristic when thethreshold voltage Vth takes a typical value. The characteristic FAST isa characteristic when the threshold voltage Vth varies at lowfrequencies. The characteristic SLOW is a characteristic when thethreshold voltage Vth varies at high frequencies. In order to realize atarget oscillation frequency 701 which meets the specifications, a widerange 702 can be used as a tuning range of the control voltage Vcntl.

While the R (resistor) 1402 of the CR ring element 1404 is variable inan analog way in FIG. 14A, Cs (capacitances) 502 a and 502 b of the CRring element 404 are variable in an analog way in the presentembodiment. The one realizing the variable capacitances 502 a and 502 bis an on-chip varactor (varicap) having a structure shown in FIG. 3.According to the varactor with this structure, when the voltages Vvar atboth ends of the varactor are variable, it becomes possible that thecapacitance Cvar of the varactor itself takes a wide range of variation,as shown in FIG. 6. A C-V (capacitance-voltage) characteristic of thevaractor is expressed by a stable first-order straight line which is inproportion to the voltage Vvar. Normally, it is ideal that the gain ofthe VCO is expressed by a linear form, but, when assuming the statewhere the PLL circuit is locked, the gain is not necessarily expressedby a perfect linear form. As described above, what becomes important inthe PLL circuit are mutually different factors, which are, to take thetuning range 702 at the maximum and to suppress the gain of the VCO. Asa supplemental explanation, since even the ring oscillator in FIG. 14Ais influenced by a nonlinearity of the transistor, the characteristicthereof is not expressed by a first-order straight line perfectly. Whatis important in the characteristic of the varactor is that there is noinfluence of the threshold voltage Vth.

As described above, by fixing the resistors (R) 402 a and 402 b andvarying the capacitances (C) 502 a and 502 b of the CR ring (delay)element 404, the range of the oscillation frequency fosc of the VCO 104can be varied in proportion to the control voltage Vcntl output from theLPF 103 without being affected by the threshold voltage Vth. In thecircuit in FIG. 14B, a control is conducted via the bias unit 1431 whichis generally composed of a current mirror circuit. The current mirrorcircuit is sensitive to the process variation, the power supply voltagevariation, or the temperature variation, so that a significantdifference of the gain of the VCO is inevitably produced. The varactors502 a and 502 b of the present embodiment have merits in that they arequite strong against these characteristics. Further, in the currentmirror circuit, an accuracy of copy is worsened as the voltage islowered, but, in the present embodiment, even being scaled to lowervoltages, all the ranges that the power supply voltage takes can be usedas a tuning range. Further, the tuning range calculated based onvariable ranges of the varactors 502 a and 502 b can be easilycalculated by manipulating the number of varactors 502 a and 502 b beinglined in parallel, which provides a merit such that the required tuningrange can be covered by a minimum gain of the VCO. As a result, a lowergain of the VCO can be achieved, and a PLL circuit with smaller jittercan be structured, as compared to the circuit in FIG. 14B.

Since the varactors 502 a and 502 b can be directly controlled by thecontrol voltage Vcntl, there is no need to provide the bias unit 1431 inFIG. 14B, which is another characteristic of the present embodiment.Since the bias unit 1431 being composed of the current mirror circuitenlarges a resistor Rds between the drain and the source of thetransistor 1412, the transistor 1412 with long gate length and largegate width is applied. Therefore, to eliminate the bias unit 1431provides a large effect in reduction of an area being used.

As described above, according to the present embodiment, in the voltagecontrolled ring oscillator which generates oscillation by applyingpositive feedback to the amplifiers, the tuning voltage range of the VCOcan be enlarged into a wide range without being affected by thethreshold voltage Vth, by controlling the voltage in an analog way inthe on-chip varactor elements 502 a and 502 b.

FIG. 8A is a block diagram showing a structural example of a PLL circuitaccording to a second embodiment of the present invention. The PLLcircuit is the same as the PLL circuit 110 in FIG. 1.

FIG. 8B is a circuit diagram showing a structural example of a VCO 104in FIG. 8A. The VCO 104 is the same as the VCO in FIG. 4.

FIG. 8C is a circuit diagram showing a structural example of a CR ringelement 404 in FIG. 8B. A point where the present embodiment isdifferent from FIG. 5 will be explained. An N-channel transistor 801corresponds to the current source 403 in FIG. 5, and having a gate, asource, and a drain respectively connected to a fixed voltage Vb, aground, and an interconnection point of sources of the transistors 501 aand 501 b. The CR ring element 404 is a CR delay element in whichresistors (R) 402 a and 402 b are fixed and capacitances (C) 502 a and502 b are variable. The CR ring element 404 has a CML-type differentialamplifier, and applies pure resistors 402 a and 402 b as loads in whichno transistors are used.

As described above, according to the present embodiment, the transistor801 serves as a current source, which flows a tail current Is of theCML-type differential amplifier. The oscillation is generated by makingthe gate voltage Vb of the transistor 801 constant, using the pureresistors 402 a and 402 b as the loads, and by using a linearity of theC-V characteristic of the variable capacitances 502 a and 502 b.

FIG. 9A is a block diagram showing a structural example of a PLL circuitaccording to a third embodiment of the present invention. The PLLcircuit is the same as the PLL circuit in FIG. 8A.

FIG. 9B is a circuit diagram showing a structural example of a VCO 104in FIG. 9A. The VCO 104 is the same as the VCO in FIG. 8B.

FIG. 9C is a circuit diagram showing a structural example of a CR ringelement 404 in FIG. 9B. A point where the present embodiment isdifferent from FIG. 8C will be explained. Load resistor units 901 a and901 b are provided in place of the load resistors 402 a and 402 b inFIG. 8C.

FIG. 9D is a view showing a structural example of the respective loadresistor units 901 a and 901 b in FIG. 9C. The load resistor units 901 aand 901 b are composed of P-channel transistors 902. The transistor 902is connected at a gate thereof to a fixed voltage Vb1, at a sourcethereof to the power supply voltage, and at a drain thereof to a drainof either the transistor 501 a or the transistor 501 b.

FIG. 9E is a view showing another structural example of the respectiveload resistor units 901 a and 901 b in FIG. 9C. The load resistor units901 a and 901 b are composed of P-channel transistors 903. Thetransistor 903 is diode-connected. Specifically, the transistor 903 isconnected at a source thereof to the power supply voltage, and at a gateand a drain thereof to the drain of either the transistor 501 a or thetransistor 501 b.

FIG. 9F is a view showing still another structural example of therespective load resistor units 901 a and 901 b in FIG. 9C. The loadresistor units 901 a and 901 b are composed of P-channel transistors 904and 905. The transistor 904 corresponds to the transistor 902 in FIG.9D. The transistor 905 corresponds to the transistor 903 in FIG. 9E. Thetransistors 904 and 905 are connected in parallel.

The present embodiment is an example where transistors are applied tothe load resistor units 901 a and 901 b. FIG. 9D shows a type in whichthe P-channel transistor 902 is directly biased. FIG. 9E shows adiode-connected type transistor 903 which is made to be strong against acommon variation by suppressing some gains. FIG. 9F shows a symmetricload type in which a linearity of the transistor is improved byconnecting the bias transistor 904 and the diode-connected transistor905 in parallel.

FIG. 10A is a block diagram showing a structural example of a PLLcircuit according to a fourth embodiment of the present invention. ThePLL circuit is the same as the PLL circuit in FIG. 8A.

FIG. 10B is a circuit diagram showing a structural example of a VCO 104in FIG. 10A. Positions of the load resistors 402 and the current sources403 in the VCO 104 are opposite to those of the VCO in FIG. 8B. Thecurrent sources 403 are connected between the power supply voltage andthe differential amplifiers 401. The load resistors 402 are connectedbetween the differential amplifiers 401 and the ground.

FIG. 10C is a circuit diagram showing a structural example of a CR ringelement 404 in FIG. 10B. A P-channel transistor 1001 corresponds to thecurrent source 403 in FIG. 10B, and has a gate, a source, and a drainrespectively connected to a fixed voltage Vb, the power supply voltage,and an interconnection point of sources of P-channel transistors 1007 aand 1007 b. A gate of the P-channel transistor 1007 a is connected to anon-inverting input terminal I+. A gate of the P-channel transistor 1007b is connected to an inverting input terminal I−. The variablecapacitance 502 a is connected between a drain of the transistor 1007 aand the control voltage Vcntl. The variable capacitance 502 b isconnected between a drain of the transistor 1007 b and the controlvoltage Vcntl. A non-inverting output terminal O+ is connected to thedrain of the transistor 1007 b. An inverting output terminal O− isconnected to the drain of the transistor 1007 a. A load resistor unit1006 a is connected between the drain of the transistor 1007 a and theground. A load resistor unit 1006 b is connected between the drain ofthe transistor 1007 b and the ground. The load resistor units 1006 a and1006 b correspond to the load resistors 402 in FIG. 10B.

FIG. 10D is a view showing a structural example of the respective loadresistor units 1006 a and 1006 b in FIG. 10C. The load resistor units1006 a and 1006 b are composed of N-channel transistors 1002. Thetransistor 1002 is connected at a gate thereof to a fixed voltage Vb1,at a source thereof to the ground, and at a drain thereof to the drainof either the transistor 1007 a or the transistor 1007 b.

FIG. 10E is a view showing another structural example of the respectiveload resistor units 1006 a and 1006 b in FIG. 10C. The load resistorunits 1006 a and 1006 b are composed of N-channel transistors 1003. Thetransistor 1003 is diode-connected. Specifically, the transistor 1003 isconnected at a source thereof to the ground, and at a gate and a drainthereof to the drain of either the transistor 1007 a or the transistor1007 b.

FIG. 10F is a view showing still another structural example of therespective load resistor units 1006 a and 1006 b in FIG. 10C. The loadresistor units 1006 a and 1006 b are composed of N-channel transistors1004 and 1005. The transistor 1004 corresponds to the transistor 1002 inFIG. 10D. The transistor 1005 corresponds to the transistor 1003 in FIG.10E. The transistors 1004 and 1005 are connected in parallel.

The present embodiment shows an example where the tail current Is isintroduced from the power supply voltage side, being different from FIG.9C. Since this circuit is mainly composed of the P-channel transistor,compared to the circuit structure in FIG. 9C, it has a demerit inlowering the band, but, it has also a merit in exhibiting a good 1/fnoise characteristic.

FIG. 11A is a block diagram showing a structural example of a PLLcircuit according to a fifth embodiment of the present invention. ThePLL circuit is the same as the PLL circuit in FIG. 8A.

FIG. 11B is a circuit diagram showing a structural example of a VCO 104in FIG. 11A. The VCO 104 is the same as the VCO in FIG. 8B.

FIG. 11C is a circuit diagram showing a structural example of a CR ringelement 404 in FIG. 11B. A point where the present embodiment isdifferent from FIG. 8C will be explained. Load resistor units 1103 a and1103 b are variable resistors, and are provided in place of the loadresistors 402 a and 402 b in FIG. 8C. A tail current source 1104 is avariable current source, and is provided instead of the transistor 801in FIG. 8C.

FIG. 11D is a view showing a structural example of the respective loadresistor units 1103 a and 1103 b in FIG. 11C. Sources and drains of aplurality of P-channel transistors 1101 are respectively connected inparallel. The transistors 1101 are connected to the power supply voltageat an interconnection point of the sources thereof, and connected to thedrain of either the transistor 501 a or the transistor 501 b at aninterconnection point of the drains thereof. A voltage is supplied fromthe outside to gates of the plurality of transistors 1101. Resistancevalues of the load resistor units 1103 a and 1103 b can be varied byweighting the plurality of transistors 1101, and by controlling therespective gate voltages individually from the outside.

FIG. 11E is a view showing a structural example of the tail currentsource 1104 in FIG. 11C. Sources and drains of a plurality of N-channeltransistors 1102 are respectively connected in parallel. The transistors1102 are connected to the ground at an interconnection point of thesources thereof, and to the source of either the transistor 501 a or thetransistor 501 b at an interconnection point of the drains thereof. Avoltage is supplied from the outside to gates of the plurality oftransistors 1102. A current amount of the tail current source 1104 canbe varied by weighting the plurality of transistors 1102, and bycontrolling the respective gate voltages individually from the outside.

According to the present embodiment, an offset frequency can becontrolled. By making the resistance values of the load resistor units1103 a and 1103 b variable from the outside, it becomes possible tochange a center oscillation frequency of the VCO 104. In order not tochange an operating point, the current amount of the tail current source1104 can also be variable in addition to the load resistor units 1103 aand 1103 b.

The variable capacitances 502 a and 502 b are controlled by the controlvoltage Vcntl. On the other hand, the transistors 1101 of the loadresistor units 1103 a and 1103 b, and the gates of the transistors 1102of the current source 1104 are controlled by a voltage independent fromthe control voltage Vcntl. In an operation preparation stage of the PLLcircuit, the load resistor units 1103 a and 1103 b and the tail currentsource 1104 are controlled from the outside, to thereby determine thecenter oscillation frequency of the VCO 104. During the operation of thePLL circuit, only the variable capacitances 502 a and 502 b arecontrolled by the control voltage Vcntl being fed back, to therebydetermine the oscillation frequency. Note that the gates of thetransistors 1102 of the current source 1104 can be controlled by thecontrol voltage Vcntl.

As described above, by connecting the transistors 1102 of the tailcurrent source 1104 in parallel, the current value of the current source1104 can be variable from the outside. Further, by connecting thetransistors 1101 of the load resistor units 1103 a and 1103 b inparallel, on-resistances of the transistors 1101 can be variable. Thesecontrols enable the VCO 104 to freely select the offset frequency.

FIG. 12A is a block diagram showing a structural example of a PLLcircuit according to a sixth embodiment of the present invention. ThePLL circuit is the same as the PLL circuit in FIG. 8A.

FIG. 12B is a circuit diagram showing a structural example of a VCO 104in FIG. 12A. The VCO 104 is the same as the VCO in FIG. 8B.

FIG. 12C is a circuit diagram showing a structural example of a CR ringelement 404 in FIG. 12B. A point where the present embodiment isdifferent from FIG. 9C will be explained. An offset capacitance 1201 ais connected in parallel with the variable capacitance 502 a, and anoffset capacitance 1201 b is connected in parallel with the variablecapacitance 502 b. The tail current source 403 corresponds to thetransistor 801 in FIG. 9C.

FIG. 12D is a view showing a structural example of the respective offsetcapacitances 1201 a and 1201 b in FIG. 12C. A plurality of variablecapacitances 1202 are connected in parallel. The capacitance 1202 mayhave a capacitance value controlled by a voltage independent from thecontrol voltage Vcntl, or it may be a fixed capacitance.

FIG. 12E is a view showing another structural example of the respectiveoffset capacitances 1201 a and 1201 b in FIG. 12C. Sources and drains ofa plurality of P-channel transistors 1203 are respectively connected inparallel with either the variable capacitance 502 a or the variablecapacitance 502 b. An external voltage independent from the controlvoltage Vcntl is supplied to gates of the plurality of transistors 1203.Capacitance values between the sources and the drains of the transistors1203 can be varied by weighting the plurality of transistors 1203, andby controlling the respective gate voltages individually from theoutside.

According to the present embodiment, an offset frequency can becontrolled. By making the capacitance values of the offset capacitances1201 a and 1201 b variable from the outside, it becomes possible tochange a center oscillation frequency of the VCO 104.

As described above, by connecting the offset capacitances 1201 a and1201 b in parallel with the variable capacitances 502 a and 502 bcapable of being controlled in an analog way, it is possible to freelyselect the offset frequency. The offset capacitances 1201 a and 1201 bmay be varactor elements, other than the analog capacitance elements andthe transistors.

According to the fifth and sixth embodiments, it is possible to easilychange the center oscillation frequency. Depending on the specificationsof the PLL circuit, the usage in which the center oscillation frequencyof the VCO is changed is conceivable. As a method for changing thecenter oscillation frequency, to vary the on-resistances as in the fifthembodiment or to add capacitances as offset capacitances as in the sixthembodiment, can be mentioned. To make the on-resistance variable, it isonly needed to connect the transistors 1101 of the load resistor units1103 a and 1103 b in parallel with each other. In this case, if thecurrent of the tail current source 1104 is also controlled in accordancewith the resistance values of the load resistor units 1103 a and 1103 b,a stable operation can be generally realized, since the operating pointdoes not change. Specifically, the on/off of the transistors 1101 of theload resistor units 1103 a and 1103 b is controlled so that the currentbeing half of the tail current flows through the respective loadresistor units 1103 a and 1103 b. Further, the center frequency can alsobe changed by connecting the offset capacitances 1201 a and 1201 b inparallel with the variable capacitances 502 a and 502 b. There is noproblem that the offset capacitances 1201 a and 1201 b are capacitanceelements using MOS structures, capacitances using varactors or wires, orthe like, other than the analog capacitance elements.

FIG. 13 is a block diagram showing a structural example of a PLL circuitaccording to a seventh embodiment of the present invention. A pointwhere this PLL circuit is different from the PLL circuit in FIG. 8A willbe explained. In FIG. 8A, the VCO 104 generates the differential signalsto output. On the other hand, in FIG. 13, the VCO 104 generates asingle-phase signal PCLK to output.

FIG. 2 is a circuit diagram showing a structural example of the VCO 104in FIG. 13. The VCO 104 is a voltage controlled ring oscillator. Aplurality of odd number of inverters (amplifiers) 201 arering-connected. The inverter 201 inverts an input signal by 180°, andamplifies it to output. A plurality of variable capacitances 202 arerespectively connected between outputs of the plurality of inverters 201and the control voltage Vcntl. The variable capacitance 202 has the samestructure as that in FIG. 3, and a capacitance value thereof varies inaccordance with the control voltage Vcntl. Since the inverter 201 hasthe on-resistance of the transistor, the VCO 104 has a CR ring element.As same as the first to sixth embodiments, by varying the variablecapacitances 202, the oscillation frequency can be controlled.

The present embodiment shows a voltage controlled ring oscillator whichapplies positive feedback by connecting an odd number of stages ofinverters 201. By connecting the variable capacitances (varactorelements) 202 formed on a semiconductor chip to the outputs of therespective inverters 201, the influence of the threshold voltage Vth canbe eliminated, and the tuning voltage range can be enlarged.

As described above, according to the first to seventh embodiments, inthe voltage controlled ring oscillator, the tuning voltage range of theVCO can be enlarged without being affected by the threshold voltage Vth.By covering the oscillation frequency range which meets thespecifications with the variable range of the variable capacitances, thegain of the VCO can be sufficiently lowered, and the PLL circuit withsmall jitter can be structured.

Further, during the operation with low power supply voltage of the PLLcircuit, the tuning voltage range can be secured without being affectedby the threshold voltage Vth. The PLL circuit can operate in the processof the characteristic TYP until the voltage reaches the low power supplyvoltage of 0.6V, which is confirmed in a simulation.

Further, the circuit structure becomes hard to be affected by theprocess variation, so that the gain of the VCO can be suppressed at 2/1or lower of that of the circuit in FIG. 14B, which enables the circuitto be strong against the power supply voltage variation, and to reducethe noise.

Further, when viewed from the PLL circuit, to reduce the gain of the VCOto half means that the capacitance of the LPF 103 is allowed to be halfin the same loop parameter, so that the area used by the PLL circuitalso becomes 2/1 (half).

Note that the present embodiments are to be considered in all respectsas illustrative and no restrictive, and all changes which come withinthe meaning and range of equivalency of the claims are thereforeintended to be embraced therein. The invention may be embodied in otherspecific forms without departing from the spirit or essentialcharacteristics thereof.

INDUSTRIAL APPLICABILITY

An oscillation frequency can be controlled without being affected by athreshold voltage of a transistor by voltage-controlling a capacitanceof a variable capacitance element. Accordingly, a wide range of voltagecontrol can be conducted, resulting that a stable oscillation can beperformed even in a case where a power supply voltage is lowered.Further, since being hard to be affected by a process variation, theoscillation can be performed stably. Furthermore, a gain can be reduced,so that a noise can be lowered.

1. A phased locked loop circuit, comprising: a phase detector to compare a feedback clock signal with a reference clock signal and to output a difference signal; a charge pump to output a signal based on the difference signal; a filter to smooth the signal and to output a voltage control signal; and a voltage controlled ring oscillator to output a clock signal corresponding to the feedback clock signal based on the voltage control signal, wherein the voltage controlled ring oscillator includes: a plurality of Current Mode Logic type (CML-type) differential amplifiers which are ring-connected; and a plurality of variable capacitance elements being respectively connected to said plurality of amplifiers and having capacitances varied by the voltage control signal, a plurality of load resistors respectively connected to said plurality of amplifiers; a plurality of tail current sources respectively connected to said plurality of amplifiers; and a plurality of offset capacitance elements respectively connected in parallel with said plurality of variable capacitance elements, a capacitance of each of the plurality of offset capacitance elements being capable of being variable-controlled independent from said variable capacitance.
 2. The phased locked loop circuit according to claim 1, wherein each of the plurality of current sources is a constant current source, and each of the plurality of load resistors is a fixed resistor.
 3. The phased locked loop circuit according to claim 2, wherein each of the plurality of load resistors is a pure resistor in which no transistor is used.
 4. The phased locked loop circuit according to claim 2, wherein a P-channel field-effect transistor is used as each of the plurality of load resistors.
 5. The phased locked loop circuit according to claim 2, wherein an N-channel field-effect transistor is used as each of the plurality of load resistors.
 6. The phased locked loop circuit according to claim 1, wherein each of the plurality of tail current sources is a variable current source, or each of the plurality of load resistors is a variable resistor.
 7. The phased locked loop circuit according to claim 1, wherein said plurality of amplifiers are an odd number of inverters, and said plurality of variable capacitance elements are respectively connected to outputs of the plurality of inverters.
 8. The phased locked loop circuit according to claim 1, wherein a field-effect transistor is used as each of the plurality of tail current sources.
 9. The phased locked loop circuit according to claim 4, wherein each of the plurality of load resistors is a P-channel field-effect transistor whose gate voltage is constant, a diode-connected P-channel field-effect transistor, or one in which the P-channel field-effect transistor whose gate voltage is constant and the diode-connected P-channel field-effect transistor are parallel-connected.
 10. The phased locked loop circuit according to claim 9, wherein an N-channel field-effect transistor is used as each of the plurality of tail current sources.
 11. The phased locked loop circuit according to claim 5, wherein each of the plurality of load resistors is an N-channel field-effect transistor whose gate voltage is constant, a diode-connected N-channel field-effect transistor, or one in which the N-channel field-effect transistor whose gate voltage is constant and the diode-connected N-channel field-effect transistor are parallel-connected.
 12. The phased locked loop circuit according to claim 11, wherein a P-channel field-effect transistor is used as each of the plurality of tail current sources.
 13. The phased locked loop circuit according to claim 6, wherein a current of each of the plurality of tail current sources is capable of being variable-controlled independent from said variable capacitance, and each of the plurality of tail current sources includes a plurality of parallel-connected field-effect transistors.
 14. The phased locked loop circuit according to claim 6, wherein a resistance of each of the plurality of load resistors is capable of being variable-controlled independent from said variable capacitance, and each of the plurality of load resistors includes a plurality of parallel-connected field-effect transistors.
 15. The phased locked loop circuit according to claim 1, wherein each of the plurality of offset capacitance elements includes a plurality of parallel-connected field-effect transistors.
 16. The phased locked loop circuit according to claim 1, wherein each of the plurality of variable capacitances is formed on a semiconductor chip. 